1. Field of the Invention
The present invention relates generally to a method for manufacturing read only memory (ROM) devices. More specifically, a method is disclosed for minimizing the product turn-around time for making semiconductor permanent store ROM cells with small cell size. This invention particularly involves the use of boron implantation through single or multi-level metal interconnections, which are formed within a ROM region.
2. Description of the Prior Art
Read-only memory (ROM), also known as firmware, is an integrated circuit programmed with specific data when it is manufactured. ROM chips are used not only, in computers, but in most other electronic items as well. The process of programming data is also referred to as coding. Hitherto, numerous coding methods have been developed to program data into the memory cells during different phases of their manufacture. One development that has gained wide use is the threshold voltage implant method, which changes a transistor""s threshold voltage by ion implanting the transistor gates for programmed cells. By way of example, for coding an N-channel memory cell, a predetermined dosage of impurities such as boron are implanted into the channel area under the gate of the transistor to raise its threshold voltage, thereby turning this memory cell into an xe2x80x9coffxe2x80x9d state.
It is often desirable to apply the ROM code onto the partially completed devices during a latter part of the manufacturing process. By applying the code at the latter part of the process, it takes less time to complete wafer processing. Customers require the product turn-around time between receipt of the ROM code for a custom order and delivery of finished parts to be kept as short as possible. Less time for completion means a shorter product turn-around time.
U.S. Pat. No. 4,268,950, filed Jun. 5, 1978 by Chatterjee et al., assigned to Texas Instruments discloses a process for making an N-channel silicon gate MOS read only memory that may be programmed at a late stage in the manufacturing process. The cell array is programmed by boron implantation through a protective nitride, polysilicon strips, and gate oxides to raise the threshold voltage of selected cells to a value above that which will be turned on by the voltage on the selected address line. According to U.S. Pat. No. 4,268,950, no metal lines are used in the cell array, only in the peripheral areas.
U.S. Pat. No. 5,514,609, filed May 13, 1994 by Chen et al., assigned to Mosel Vitelic discloses the manufacture of a ROM cell that is coded before metallization. ROM code impurities are implanted first through a dielectric layer overlying gate electrodes, and then through the underlying selected gate electrodes.
U.S. Pat. No. 6,020,241, filed Dec. 22, 1997 by You et al., assigned to Taiwan Semiconductor Manufacturing Company discloses a method of manufacturing a ROM that is code implanted late in the process after the first level metal thus reducing the turn-around time to ship a customer order. It is noted that the first level metal is not formed in the cell areas, but is formed over the peripheral areas. The code implantation implants impurities through a first dielectric layer overlying gates and a second dielectric layer overlying the first dielectric layer, and through a portion of the word lines.
For today""s high-density ROM device, to reach a highest packing density, some metal interconnections such as bit lines are inevitably formed within the memory array area overlying word lines, instead of buried diffusion bit lines in the substrate as disclosed in the prior art, which occupy a lot of chip area. However, none of the above-mentioned prior art references teaches a method capable of coping with difficulties that occur when coding a ROM integrated circuit device having multilevel metal interconnections formed within the ROM region or cell array area while maintaining a short product turn-around time.
It is therefore a primary objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices that may be programmed at a selected level of multilevel metal interconnections that are formed within the ROM region, thereby shortening the product turn-around time.
It is a further objective of this invention to provide a method for manufacturing high-density read only memory (ROM) devices that involves the use of relatively high energy ion implantation to program selected transistors though multilevel metal interconnections, Inter-layer dielectric (ILD), polysilicon gates, and gate oxides.
Briefly summarized, the preferred embodiment of the present invention discloses a method for manufacturing a read only memory (ROM) device capable of shortening product turn-around time. The ROM device includes a semiconductor substrate having thereon an array of enhancement-mode metal-oxide-semiconductor field-effect transistors (MOSFETs) within a ROM region and a first dielectric layer covering the MOSFETs within the ROM region. Each of the MOSFETs has a polysilicon gate, a source, a drain, and a gate oxide between the polysilicon gate and the substrate. All of the MOSFETs are initially in a logic xe2x80x9c0xe2x80x9d, state at a first threshold voltage. After planarizing the first dielectric layer, m layers of metal interconnections are formed over the first dielectric layer within the ROM region. According to the first preferred embodiment of the present invention, the top layer of the m layers of metal interconnections (m-th layer metal) within the ROM region is further covered by a top inter-metal dielectric (IMD) layer corresponding to the IMD layer of the m+1 layer metal interconnection that is fabricated in the peripheral area. According to the second preferred embodiment of the present invention, the top layer of the m layers of metal interconnections is covered by a plurality of IMD layers each of which corresponds to one of the IMD layers from the m+1 layer to the Xth layer metal interconnections that are fabricated in the peripheral area.
In accordance with the first preferred embodiment of the present invention, the method generally includes the steps of: forming a mask layer on the top IMD layer, the mask layer having an opening exposing the entire ROM region; etching away a thickness of the top IMD layer through the opening without exposing the top layer of the m layers of metal interconnections to form a recess over the ROM region; removing the mask layer; forming a coding photoresist layer on the remaining top IMD layer in the recess; patterning the coding photoresist layer to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the logic xe2x80x9c0xe2x80x9d state into a logic xe2x80x9c1xe2x80x9d state; using the patterning coding photoresist layer as an implant hard mask to implant the underlying MOSFETs to be coded through the apertures, m layers of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby transforming the MOSFETs to be coded into the logic xe2x80x9c1xe2x80x9d state at a second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage; and stripping the coding photoresist layer.
In accordance with the second preferred embodiment of the present invention, the method includes forming a mask layer on the plurality of IMD layers. The mask layer has an opening exposing the entire ROM region. A thickness of the plurality of IMD layers is etched away through the opening without exposing the top layer of the m layers of metal interconnections to form a recess over the ROM region. The mask layer is removed. A coding photoresist layer is formed on the remaining top IMD layer in the recess. The coding photoresist layer is then patterned to form a plurality of apertures defining exposure windows where the underlying MOSFETs are to be coded from the logic xe2x80x9c0xe2x80x9d state into a logic xe2x80x9c1xe2x80x9d state. The patterning coding photoresist layer is used as an implant hard mask to implant the underlying MOSFETs to be coded through the apertures, m layers of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby transforming the MOSFETs to be coded into the logic xe2x80x9c1xe2x80x9d state at a second threshold voltage, wherein the second threshold voltage is higher than the first threshold voltage; and stripping the coding photoresist layer.
According to one aspect of the present invention, an alternative method for manufacturing a ROM device is disclosed. A semiconductor substrate having thereon an array of field-effect transistors within a ROM region is provided. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an xe2x80x9cONxe2x80x9d state having a threshold voltage at a first value. Over the first dielectric layer within the ROM region, m layers of metal interconnections are formed. The m layers of metal interconnections are further covered by composite dielectric layers. The composite dielectric layers are introduced for the remaining metal isolation after m-th layer are formed in the peripheral area. The device is held awaiting the details of a custom""s order, which will determine the exact configuration of the code implantation. A coding photoresist layer is then formed on the composite dielectric layers. The coding photoresist layer is patterned to form a plurality of apertures defining exposure windows where the underlying field-effect transistors are to be coded permanently to an xe2x80x9cOFFxe2x80x9d state. Using the patterned coding photoresist layer as a dielectric etching mask and also animplant hard mask, a thickness of the composite dielectric layers is etched away through the apertures, and the underlying field-effect transistors to be coded are then code implanted through the apertures, the layer of metal interconnections, polysilicon gates, and gate oxides into the substrate, thereby raising the threshold voltage of the field-effect transistors to be coded to a second value.
In short, according to the present invention, the ROM code implantation may be accomplished through either a 2-mask procedure or a single-mask procedure. The 2-mask procedure includes the use of a first mask defining one big opening through which the composite dielectric is etched back to the m-th layer. The second mask is used to pattern the ROM code with many small openings. Each small opening represents a program address for each individual ROM memory cell to logic xe2x80x9c1xe2x80x9d state. Alternatively, the ROM code implantation may be accomplished through single-mask procedure, in which the ROM code is defined with many small openings omitting the first mask. This means that etching of the dielectric and code implanting are carried out through the same code openings. It is advantageous to use the 2-mask procedure since the product turn-around time is shorter than that of using single-mask procedure. After etching the composite dielectric with the first mask,the ROM device is stored and kept in the state awaiting the customer code mask. There is no etching step after receiving the customer code mask. On the other hand,the single-mask method requires both etch and implantation with the same mask after receiving the customer code mask. It is a trade off when choosing one between the 2-mask and single-mask methods because using single-mask method results in reduced cost (only one mask) but relatively longer turn around time.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.